module FDPE_rtl (
    input       C ,
    input       CE ,
    input       PRE ,
    input       D ,
    output reg  Q
) ;

    wire CLK ;
    // PREICG_X9B_A12PP140ZTL_C30 clk_gate ( .CK(C), .E(CE), .SE(1'b0), .ECK(CLK) );
    PREICG_X1B_A12PP140ZTS_C35 clk_gate ( .CK(C), .E(CE), .SE(1'b0), .ECK(CLK) );
    // assign CLK = C & CE;
    always @(posedge CLK or posedge PRE) begin
        if( PRE )
            Q <= 1'b1 ;
        else if( CE )
            Q <= D ;
    end

endmodule
